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d a t a sh eet objective speci?cation supersedes data of 1997 mar 03 file under integrated circuits, ic22 1998 feb 05 integrated circuits SAA5284 multimedia video data acquisition circuit
1998 feb 05 2 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 contents 1 features 2 general description 3 quick reference data 4 ordering information 5 main functional blocks 6 block diagram 7 pinning information 7.1 pinning 7.2 pin description 8 functional description 8.1 power supply strategy 8.2 clocking strategy 8.3 power-on reset 8.4 analog switch 8.5 analog video-to-data byte converter 8.6 packet filtering 8.7 packet buffer 8.8 fifo 8.9 host interface 8.10 interrupt support 8.11 dma support 8.12 i 2 c-bus interface 9 limiting values 10 quality & reliability 11 characteristics 12 timing 13 application information 13.1 hardware application circuit for isa card 13.2 hardware application circuit for pci application 13.3 software application information 14 package outline 15 soldering 15.1 introduction 15.2 reflow soldering 15.3 wave soldering 15.4 repairing soldered joints 16 definitions 17 life support applications 18 purchase of philips i 2 c components
1998 feb 05 3 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 1 features high performance multi-standard data slicer intercast ? (intel corporation) compatible teletext (wst, chinese teletext) (625 lines) teletext (us teletext, nabts and moji) (525 lines) wide screen signalling (wss), video programming signal (vps) closed caption (europe, us) data broadcast, pdc (packet 30 and 31) user programmable data format (programmable framing code) 2 kbytes data cache on-chip to avoid data loss and reduce host cpu overhead filtering of packets 30 and 31 wst/nabts choice of clock frequencies, direct-in clock or crystal oscillator parallel interface, motorola, intel and digital video bus i 2 c-bus control data transport by digital video bus choice of programmable interrupt, dma or polling driven data type selectable video line by video line, with vertical blanking interval and full field mode single ic with few external components and small footprint qfp44 package optimized for emc. 2 general description the SAA5284 is a vertical blanking interval (vbi) and full field (ff) video data acquisition device tailored for application on pc add-in cards, pc mother-boards, set-top boxes and as a saa5250 replacement. the ic in combination with a range of software modules will acquire most existing formats of broadcast vbi and ff data. these associated software modules are available under licence. scope is provided for acquiring some as yet unspecified formats. the SAA5284 incorporates all the data slicing, parallel interface, data filtering and control logic. it is controlled either by a parallel interface or i 2 c-bus. it can output ascii vbi data as pixels on the digital video bus where no parallel port is available. it is available in a qfp44 package. 3 quick reference data note 1. selectable: 12, 13.5, 15 or 16 mhz. 4 ordering information symbol parameter min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v i dd supply current - 72 95 ma v sync(p-p) sync voltage (peak-to-peak value) 0.1 0.3 0.6 v v i(cvbs)(p-p) input voltage on pin cvbs0 and cvbs1 (peak-to-peak value) 0.7 1.0 1.4 v f xtal crystal frequency; see note 1 - 12.0 - mhz t amb operating ambient temperature - 20 - +70 c type number package name description version SAA5284gp qfp44 plastic quad ?at package; 44 leads (lead length 2.35 mm); body 14 14 2.2 mm sot205-1
1998 feb 05 4 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 5 main functional blocks 1. input clamp and sync separator 2. analog-to-digital converter 3. multi-standard data slicer and clock regenerator 4. packet filtering; (8 and 4) hamming correction 5. on-chip data cache 6. line selectable data type 7. 12, 13.5, 15 and 16 mhz clock or oscillator options 8. fifo access to data 9. interrupt and dma support 10. multi-standard parallel interface 11. i 2 c-bus interface 12. power-on reset. figure 1 shows a block diagram of the SAA5284. 6 block diagram fig.1 block diagram. handbook, full pagewidth mgg740 analog switch SAA5284 multi-standard host interface i 2 c-bus interface 400 khz slave fifo packet buffer and front end control registers packet filtering (e.g. wst packets 30/31) analog video to data byte converter (data demodulator) oscillator and timing oscout oscgnd oscin packet buffer ram 2 kbyte (45 packets) 35 44 31 32 10 33 34 42 43 2 39 38 36 37 11 3 sda scl 4 5 30 to 28 20 to 27 wr (1) 16 15 14 v dda v ssa v ddx v ddd v ssd3 reset 17 6 41 40 1 vpoin0 href vpoin1 llc llc2 rd (1) dmack (1) dmarq cvbs0 cvbs1 v ssd1 v ssd2 data path control 13 12 789 18 19 i ref black 8 3 d7 to d0 (1) a2 to a0 (1) rdy (1) sel1 sel0 int cs1 denb cs0 (1) multi-functional pins, see chapter 7.
1998 feb 05 5 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 7 pinning information 7.1 pinning 7.2 pin description table 1 qfp44 package the ic has a total of 44 pins; many of these are multi-functional due to the multiple host block modes of operation. symbol pin i/o description reset 1 i reset ic href 2 i video horizontal reference signal (digital video mode only) sda 3 i/o serial data port for i 2 c-bus, open-drain scl 4 i serial clock input for i 2 c-bus denb 5 o data enable bar (for external buffers) v ddx 6 - +5 v supply oscout 7 o oscillator output oscin 8 i oscillator input fig.2 pin configuration. (1) multi-functional pin. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 SAA5284 mgg739 wr (1) rdy (1) int a2 (1) a0 (1) d0 (1) d1 (1) d2 (1) d3 (1) d4 (1) reset href sda scl denb v ddx oscin oscgnd sel1 a1 (1) llc2 llc v ddd v ssd3 vpoin1 vpoin0 dmarq cs0 rd (1) cs1 dmack (1) i ref cvbs1 cvbs0 v dda v ssa v ssd1 d7 (1) d6 (1) d5 (1) black v ssd2 oscout sel0
1998 feb 05 6 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 note 1. these pins have two functions, depending on the interface mode. oscgnd 9 - oscillator ground sel0 10 i parallel interface format select 0 sel1 11 i parallel interface format select 1 black 12 i/o video black level storage; connected to v ssa via 100 nf capacitor i ref 13 i reference current input; connected to v ssa via 27 k w resistor cvbs1 14 i analog composite video input 1 cvbs0 15 i analog composite video input 0 v dda 16 - analog +5 v supply v ssa 17 - analog ground supply v ssd1 18 i digital ground supply 1 v ssd2 19 i digital ground supply 2 d7 (1) 20 i/o data bus 7/video data output 7 d6 (1) 21 i/o data bus 6/video data output 6 d5 (1) 22 i/o data bus 5/video data output 5 d4 (1) 23 i/o data bus 4/video data output 4 d3 (1) 24 i/o data bus 3/video data output 3 d2 (1) 25 i/o data bus 2/video data output 2 d1 (1) 26 i/o data bus 1/video data output 1 d0 (1) 27 i/o data bus 0/video data output 0 a0 (1) 28 i address input 0/video data input 7 a1 (1) 29 i address input 1/video data input 6 a2 (1) 30 i address input 2/video data input 5 int 31 o interrupt request rdy (1) 32 o ready/dtack (data acknowledge)/vbi, open-drain wr (1) 33 i intel bus write/motorola bus r/ w/video data input 4 rd (1) 34 i intel bus read/motorola bus lds/video data input 3 cs0 35 i chip select 0; active low dmarq 36 o dma request dmack (1) 37 i dma acknowledge/video data input 2 vpoin0 38 i video data input 0 vpoin1 39 i video data input 1 v ssd3 40 - digital ground supply 3 v ddd 41 - digital +5 v supply llc 42 i full rate digital video clock input llc2 43 i half rate digital video clock input cs1 44 i chip select 1; active low symbol pin i/o description
1998 feb 05 7 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 8 functional description 8.1 power supply strategy there are three separate +5 v (v dd ) connections to the ic: 1. v dda supplies the critical noise-sensitive analog front-end sections: adc and sync separator, to reduce interference from the rest of the front-end 2. v ddx supplies all sections which take standing dc current 3. v ddd supplies the rest of the logic. 8.2 clocking strategy the master frequency reference for the ic is a 12, 13.5, 15 or 16 mhz crystal oscillator. the tolerance on the clock frequency is 500 10 - 6 (1.5 khz). further speci?cations of the crystal are given in table 2. if preferred, an external 12, 13.5, 15 or 16 mhz ( 1.5 khz) frequency source may be connected to oscin instead of the crystal. 8.3 power-on reset the reset pin should be held high for a minimum of two clock cycles. the reset signal is passed through a schmitt trigger internally. direct addressed registers (i.e. those addressed using the a0 to a2 pins) are set to 00h after power-up. all other register bits are assumed to be in random states after power-up. 8.4 analog switch register bit selection between two video sources. 8.5 analog video-to-data byte converter this section comprises a line and field sync separator, a video clamp, an adc and a custom adaptive digital filter with dpll based timing circuit. the analog video-to-data byte converter is specifically designed to overcome the most commonly found types of distortion of a broadcast video signal. it is also fully multi-standard. the data type to be demodulated is programmable on a line-by-line basis using 4 register bits per line for lines 2 to 23 (pal numbering), fields 1 and 2, and 4 further bits for all lines combined. 8.6 packet ?ltering if using a slow (e.g. 80c51) microcontroller, it is necessary to reduce the amount of data acquired by SAA5284 before downloading to the microcontroller to avoid it being swamped by unwanted data. packet filtering is available for this purpose. a common use of this would be to acquire only packet 8/30 in 625-line wst. the packet filter includes optional (8, 4) hamming correction. 8.7 packet buffer this is a 2 kbyte ram which acts as a buffer for storing received packets. the first 44 bytes are reserved for control information. the rest of the ram is divided into 44-byte rows (or packets), each holding the data received on one incoming cvbs line. in the case of a wst packet received, the data stored consists of a magazine and row-address group (2 bytes), followed by the 40 bytes of packet data. when data in other formats than wst is received, this is stored in the packet buffer in the same way. in each case, the data is preceded by two information bytes which record on which line and field the packet was received, and what the data type is. 8.8 fifo fifo hardware is provided to manage the read address for the host processor, i.e. data is read repeatedly from the same 8-bit port, and appears byte-serially in the order of reception. the read address can be reset to the start of the packet buffer (the first 44-byte packet), back to the start of the current packet, or incremented to the start of the next packet. table 2 crystal characteristics symbol parameter min. typ. max. unit c1 series capacitance - 18.5 - ff c2 parallel capacitance - 4.9 - pf r r resonant resistance -- 50 w x a ageing -- 5 10 - 6 per year x j adjustment tolerance -- 25 10 - 6 - x d drift -- 25 10 - 6 -
1998 feb 05 8 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 8.9 host interface the SAA5284 has a multi-standard 8-bit i/o interface. to reduce the amount of host i/o space used, the parallel interface has only 3 address inputs (a0, a1 and a2). an extended addressing (pointer) scheme and the data fifo are used to allow access to the full set of SAA5284 registers and the full span of the packet buffer. as well as the 8 data i/o lines and 3 address lines, there are the following control signals: rd (read low), wr (write low), cs0 (chip select low), cs1(second chip select low), int (interrupt request), dmarq (dma request), dmack (dma acknowledge) and rdy (ready). in order to maintain compatibility with motorola and intel type buses, two control signals sel0 and sel1 are provided to configure the host interface. these signals allow configuration of the host interface to work with the motorola or intel style interfaces. the host interface has a digital video mode. digital video mode may be used to allow the SAA5284 to pass decoded vbi data into a system using the digital video bus. 8.10 interrupt support the host interface provides comprehensive support for interrupt generation. the interrupt may be programmed to occur when a particular number of packets of vbi data are available in the cache ram. the interrupts can be further controlled to occur on a specific line in the tv frame. the interrupts can also be self masking if required. 8.11 dma support burst and demand mode dma are supported. in burst mode, the number of packets to transfer can be defined. an interrupt can be generated when dma is finished. this can be self masking. 8.12 i 2 c-bus interface the i 2 c-bus interface functions as a slave receiver or transmitter at up to 400 khz. the i 2 c-bus address is selectable as 20h or 22h. all functionality is available using the i 2 c-bus although with a slower data transfer speed. it is possible to use the i 2 c-bus in all modes. 9 limiting values in accordance with the absolute maximum rating system (iec 134). 10 quality & reliability in accordance with snw-fq-611-e . symbol parameter min. max. unit v dd supply voltage (all supplies) - 0.3 +6.5 v v i(max) input voltage (any input) - 0.3 v dd + 0.5 v v o(max) output voltage (any output) - 0.3 v dd + 0.5 v d v ddd - dda - ddx supply voltage difference between v ddd , v dda and v ddx - 0.25 v i iok dc input or output diode current - 20 ma i o(max) output current (any output) - 10 ma t stg storage temperature - 55 +125 c t amb operating ambient temperature - 20 +70 c
1998 feb 05 9 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 11 characteristics t amb = - 20 to +70 c; v dd = 4.5 to 5.5 v; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit power supply v ddn supply voltage 4.5 5.0 5.5 v i dd(tot) total supply current - 72 95 ma i ddd digital supply current - 32 42 ma i dda analog supply current - 40 53 ma inputs cvbs0 and cvbs1 v sync(p-p) sync voltage (peak-to-peak value) 0.1 0.3 0.6 v v burst(p-p) colour burst voltage (peak-to-peak value) 0 0.3 0.4 v v i(vid)(p-p) video input voltage (peak-to-peak value) 0.7 1.0 1.4 v v i(data)(p-p) teletext data input voltage (peak-to-peak value) 0.29 0.46 0.71 v z source source impedance -- 250 w v i(sw) input switching level of sync separator 1.5 1.8 2.1 v z i input impedance 2.5 5.0 - k w c i input capacitance -- 10 pf input i ref r iref external resistor to v ssa - 27 - k w inputs reset, href, sel0, sel1, a0, a1, a2, wr, rd, cs0, cs1, dmack, vpoin1, vpoin0, llc and llc2 v il low-level input voltage - 0.3 - +0.8 v v ih high-level input voltage 2.0 - v dd + 0.5 v i li input leakage current v i = 0 to v dd - 10 - +10 m a c i input capacitance -- 10 pf input scl v il low-level input voltage - 0.5 - +1.5 v v ih high-level input voltage 3.0 - v dd + 0.5 v i li input leakage current v i = 0 to v dd - 10 - +10 m a c i input capacitance - 10 pf t i(r) input rise time v il(min) to v ih(max) ; f i(scl) = 100 khz 50 - 1000 ns v il(min) to v ih(max) ; f i(scl) = 400 khz 50 - 300 ns t i(f) input fall time v il(max) to v ih(min) ; f i(scl) = 100 khz 50 - 300 ns v il(max) to v ih(min) ; f i(scl) = 400 khz 50 - 300 ns f i(scl) input clock frequency 0 - 400 khz c l load capacitance -- 400 pf
1998 feb 05 10 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 input/output sda (open-drain) v il low-level input voltage - 0.5 - +1.5 v v ih high-level input voltage 3.0 - v dd + 0.5 v i li input leakage current v i =0tov dd - 10 - +10 m a c i input capacitance - 10 pf t i(r) input rise time v il(min) to v ih(max) ; f i(scl) = 100 khz 50 - 1000 ns v il(min) to v ih(max) ; f i(scl) = 400 khz 50 - 300 ns t i(f) input fall time v il(max )tov ih(min) ; f i(scl) = 100 khz 50 - 300 ns v il(max) to v ih(min) ; f i(scl) = 400 khz 50 - 300 ns v ol low-level output voltage i ol = 3 ma 0 - 0.4 v i ol = 6 ma 0 - 0.6 v t o(f) output fall time between 3 and 1.5 v; i ol =3ma 50 - 250 ns c l load capacitance -- 400 pf input/output black c black storage capacitance to v ssa - 100 - nf inputs/outputs d7 to d0 v il low-level input voltage - 0.3 - +0.8 v v ih high-level input voltage 2.0 - v dd + 0.5 v i li input leakage current v in = 0 to v dd - 10 - +10 m a c i input capacitance -- 10 pf v ol low-level output voltage i ol = +1.6 ma 0 - 0.4 v v oh high-level output voltage i oh = - 0.2 ma 2.4 - v dd v c l load capacitance -- tbf pf t o(r) output rise time into c l 0.6 to 2.2 v -- tbf ns t o(f) output fall time into c l 2.2 to 0.6 v -- tbf ns outputs int, denb and dmarq v ol low-level output voltage i ol = +1.6 ma 0 - 0.4 v v oh high-level output voltage i oh = - 0.2 ma 2.4 - v dd v c l load capacitance -- tbf pf t o(r) output rise time into c l 0.6 to 2.2 v -- tbf ns t o(f) output fall time into c l 2.2 to 0.6 v -- tbf ns rdy (open-drain) ; note 1 v ol low-level output voltage i ol = +1.6 ma 0 - 0.4 v c l load capacitance -- tbf pf t o(r) output rise time into c l 0.6 to 2.2 v -- tbf ns t o(f) output fall time into c l 2.2 to 0.6 v -- tbf ns symbol parameter conditions min. typ. max. unit
1998 feb 05 11 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 notes 1. esd protection of this pin falls below the philips general quality specification (gqs). therefore it is recommended that a diode is connected from pin rdy to v ddd . 2. the i 2 c-bus interface pins sda and scl may pull the data and clock lines below 3 v while the digital power supply v ddd is in the range 0.4 to 0.8 v. i 2 c-bus timings (see note 2 and fig.8) f i(scl) scl input clock frequency f i(scl) = 100 khz 0 - 100 khz f i(scl) = 400 khz 0 - 400 khz t low scl low time f i(scl) = 100 khz 4.7 -- m s f i(scl) = 400 khz 1.3 -- m s t high scl high time f i(scl) = 100 khz 4.0 -- m s f i(scl) = 400 khz 0.6 -- m s t su;dat data set-up time f i(scl) = 100 khz 250 -- ns f i(scl) = 400 khz 100 -- ns t hd;dat data hold time f i(scl) = 100 khz 0 -- m s f i(scl) = 400 khz 0 -- m s t su;sto set-up time stop condition f i(scl) = 100 khz 4.7 -- m s f i(scl) = 400 khz 0.6 -- m s t buf bus free time f i(scl) = 100 khz 4.7 -- m s f i(scl) = 400 khz 1.3 -- m s t hd;sta hold time start condition f i(scl) = 100 khz 4.0 -- m s f i(scl) = 400 khz 0.6 -- m s t su;sta set-up time repeated start f i(scl) = 100 khz 4.7 -- m s f i(scl) = 400 khz 0.6 -- m s t r rise time (sda and scl) f i(scl) = 100 khz -- 1000 ns f i(scl) = 400 khz -- 300 ns t f fall time (sda and scl) f i(scl) = 100 khz -- 300 ns f i(scl) = 400 khz -- 300 ns symbol parameter conditions min. typ. max. unit
1998 feb 05 12 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 12 timing fig.3 intel mode interface read cycle timing. handbook, full pagewidth mgk145 d7 to d0 a2 to a0 rd rdy cs0 or cs1 t 1 t 5 t 6 t 3 t 7 t 2 t 4 t 0 valid address valid data b (2) a (1) 3-state 3-state (1) event a occurs when rd + cs0 + cs1 = 0 (boolean). (2) event b occurs when rd + cs0 + cs1 = 1 (boolean). table 3 intel-mode interface read cycle timing (12 mhz clock) symbol description min. max. unit t 0 minimum cycle time 333 833 ns t 1 address set-up time before event a 0 - ns t 2 address hold time after event b 0 - ns t 3 data settling time 88 712 ns t 4 data hold time after event b 0 - ns t 5 time from event a until rdy goes low 83 170 ns t 6 rdy low time 83 530 ns t 7 event b to next event a time 83 - ns
1998 feb 05 13 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 fig.4 intel mode interface write cycle timing. handbook, full pagewidth mgk146 d7 to d0 a2 to a0 wr rdy cs0 or cs1 t 1 t 5 t 6 t 3 t 2 t 4 t 0 b (2) a (1) t 7 valid address valid data (1) event a occurs when wr + cs0 + cs1 = 0 (boolean). (2) event b occurs when wr + cs0 + cs1 = 1 (boolean). table 4 intel-mode interface write cycle timing (12 mhz clock) note 1. legacy at bus pcs may not satisfy this requirement as they are not isa compatible. an application fix is available in the SAA5284 users guide . symbol description min. max. unit t 0 minimum cycle time 333 833 ns t 1 address set-up time 0 - ns t 2 address hold time 0 - ns t 3 data set-up time, note 1 0 - ns t 4 data hold time 0 - ns t 5 rdy set-up time 83 170 ns t 6 rdy low time 83 530 ns t 7 event b to next event a time 83 - ns
1998 feb 05 14 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 handbook, full pagewidth mgk147 t 7 t 2 t 5 t 3 t 6 t 4 t 1 d7 to d0 rd (1) dmack dmarq valid data valid data cs (same signal as dmack) fig.5 intel mode interface dma cycle timing. (1) read data pipelined, so no rd low to data valid set-up time. table 5 intel-mode interface dma cycle timing (12 mhz clock) note 1. this timing will be up to 3 clock cycles for the first read in dma transfer. symbol description min. max. unit t 1 dmarq to dmack 0 - ns t 2 rd low to dmarq low 0 212 ns t 3 cycle time 252 - ns t 4 dmack to rd active - 0ns t 5 data set-up time 0 90 (1) ns t 6 data hold time 83 - ns t 7 data hold from dmack high 0 83 ns
1998 feb 05 15 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 fig.6 motorola mode interface read cycle timing. (1) event a occurs when lds + cs0 + cs1 = 0 (boolean). (2) event b occurs when lds + cs0 + cs1 = 1 (boolean). handbook, full pagewidth mgk148 d7 to d0 a2 to a0 lds a (1) b (2) dtack t 1 t 2 t 6 t 4 t 5 t 3 t 7 t 0 valid address valid data 3-state 3-state r/w cs1 or cs0 table 6 motorola-mode interface read cycle timing (12 mhz clock) symbol description min. max. unit t 0 minimum cycle time 333 833 ns t 1 address set-up time before event a 0 - ns t 2 address hold time after event b 0 - ns t 3 data hold time from event b 0 - ns t 4 data settling time 88 712 ns t 5 data valid to dtack low 83 170 ns t 6 lds high to dtack high 83 212 ns t 7 delay between cycles 83 - ns
1998 feb 05 16 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 fig.7 motorola mode interface write cycle timing. handbook, full pagewidth mgk149 d7 to d0 a2 to a0 lds a (1) b (2) dtack t 1 t 2 t 6 t 4 t 5 t 3 t 0 valid address valid data 3-state 3-state r/w cs1 or cs0 t 7 (1) event a occurs when lds + cs0 + cs1 = 0 (boolean). (2) event b occurs when lds + cs0 + cs1 = 1 (boolean). table 7 motorola-mode interface write cycle timing (12 mhz clock) symbol description min. max. unit t 0 minimum cycle time 333 417 ns t 1 address set-up time before event a 0 - ns t 2 address hold time after event b 0 - ns t 3 data hold time from event b 0 - ns t 4 data set-up time 0 - ns t 5 dtack set-up time - 212 ns t 6 lds high to dtack high 83 212 ns t 7 delay between cycles 83 - ns
1998 feb 05 17 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 fig.8 i 2 c-bus timing diagram. handbook, full pagewidth mgg741 scl sda t su;sta t buf t su;dat t high t low t hd;dat t r t f t su;sto t hd;sta fig.9 digital video mode interface timing. handbook, full pagewidth mgk150 vpoin vpoout llc llc2 t 0 t 1 t 4 t 2 t 3 cs0 or cs1 table 8 digital video mode interface timing with 13.5 mhz clock and 27 mhz llc symbol description min. typ. max. unit t 0 vpoin set-up time 4 5 6 ns t 1 vpoout set-up time 8 10 22 ns t 2 cs high to vpoout 3-state 6 10 25 ns t 3 cs low to vpoout enabled 9 11 16 ns t 4 clock quali?er set-up time - 1.1 - ns
1998 feb 05 18 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 13 application information 13.1 hardware application circuit for isa card a typical application circuit diagram (for the isa card application) is shown in fig.10. 13.2 hardware application circuit for pci application this pci application is based around the philips saa7146 video to pci bridge ic. saa7146 has a data expansion bus interface (debi) which is an intel/motorola style 16-bit parallel interface. this is used to facilitate communications to SAA5284. the application circuit diagram is shown in fig.11. 13.3 software application information pc application software is available providing two levels of interface. at a low level a vxd based driver offers generic packet gathering and buffering. full support is provided for isa based applications with facility for pci based applications. higher level support is provided by a series of dlls. these perform normal teletext display generation and page management.
1998 feb 05 19 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 fig.10 application circuit diagram for isa card. (1) option of 13.5, 15 and 16 mhz or direct feed from external clock. (2) a diode to v ddd is recommended for esd protection. (3) pin dmack must be connected to v ddd if dma is not used. handbook, full pagewidth mgg742 75 w 75 w 27 k w 22 pf 100 nf black i ref v ssa v ssd3 v ssd1 v ssd2 v ssa = 0 v v ssd = 0 v v ssd = 0 v supply decoupling sel1 sel0 cs1 cvbs0 cvbs1 oscin oscout oscgnd sda scl href llc llc2 vpoin1 vpoin0 100 nf cvbs0 cvbs1 100 nf 12 mhz (1 ) 12 16 41 6 13 15 14 8 7 9 3 4 2 42 43 39 38 17 40 18 19 11 10 gnd address decoder e.g. plus153 or 74 series logic v cc 44 22 pf v ssa = 0 v v dda = + 5 v v dda v ddd v ddx v ddd = + 5 v v ssa = 0 v d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 a0 a1 a2 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 1 5 35 2 b9 b8 b7 b6 b5 n.c. b4 b3 b2 1 int rdy (2) wr rd dmarq dmack (3) 3 4 5 6 7 8 19 11 b1 9 b0 i0 aen i1 i2 i3 i4 i5 i6 i7 a3 a4 a5 a6 a7 a8 a9 18 17 16 15 14 13 12 10 20 reset denb a0 a1 a2 irqx i/o rdy iow ior dackx reset n.c. cs0 SAA5284 v ssd = 0 v v ddd = 5 v v dda v ddd v ssa v ssd 100 nf 100 nf 10 m f 10 m f + 5 v 0 v
1998 feb 05 20 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mgg744 75 w 75 w 27 k w 22 pf 100 nf black i ref v ssa v ssd3 v ssd1 v ssd2 v ssa = 0 v v ssd = 0 v v ssd = 0 v sel1 sel0 cs1 cvbs0 cvbs1 oscin oscout oscgnd sda supply decoupling scl href llc llc2 vpoin1 vpoin0 100 nf cvbs0 cvbs1 100 nf 12 mhz (1 ) 12 16 41 6 13 15 14 8 7 9 3 4 2 42 43 39 38 17 40 18 19 11 10 44 22 pf v ssa = 0 v v dda = + 5 v v dda v ddd v ddx v ddd = + 5 v v ssa = 0 v 5 k w v ddd d7 d6 d5 d4 d3 d2 d1 d0 a0 a1 a2 1q 2q 3q 1d 2d 3d 4d 20 21 22 23 24 25 26 27 28 29 30 16 15 74hct75 10 2 3 6 7 13 4 le le 31 32 33 34 36 37 1 5 int rdy wr rd dmarq dmack reset n.c. v ddd n.c. denb SAA5284 xad7 xad6 xad5 xad4 xad3 xad2 xad1 xad0 debi port xirq rdy wrn rdn reset 23 saa7145 saa7146 115 116 117 118 35 cs0 ale 114 124 123 125 126 129 130 131 132 v dda v ddd v ssa v ssd 100 nf 100 nf 10 m f 10 m f + 5 v 0 v fig.11 application circuit diagram for pci application. (1) option of 13.5, 15 and 16 mhz or llc2 from the saa7111 if in 13.5 mhz mode.
1998 feb 05 21 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 14 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 19.2 18.2 2.4 1.8 7 0 o o 0.15 2.35 0.1 0.3 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 2.0 1.2 sot205-1 95-02-04 97-08-01 d (1) (1) (1) 14.1 13.9 h d 19.2 18.2 e z 2.4 1.8 d b p e q e a 1 a l p detail x l (a ) 3 b 11 y c d h b p e h a 2 v m b d z d a z e e v m a x 1 44 34 33 23 22 12 133e01a pin 1 index w m w m 0 5 10 mm scale qfp44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm sot205-1 a max. 2.60
1998 feb 05 22 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 15 soldering 15.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 15.2 re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. 15.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all qfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 feb 05 23 philips semiconductors objective speci?cation multimedia video data acquisition circuit SAA5284 16 definitions 17 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 18 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2870, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 655102/00/02/pp24 date of release: 1998 feb 05 document order number: 9397 750 02768

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